Digital Logic Testing and Simulation Second Edition

ion. Streamlining the code can sometimes produce a significant improve-ment in simulation performance. 12.3.2 HDL Extensions and C++ There is a growing acceptance of high-level languages (HLLs), particularly C andC++, for conceptual or system level modeling. One reason for this is the fact that amodel expressed in an HLL usually executes more rapidly than the same modelexpressed in an RTL language. This is based, at least in part, on the fact that when aVerilog or VHDL model is executing as compiled code, it is first translated into C orC++. This intermediate translation may introduce inefficiencies that the systemengineer hopes to avoid by directly encoding his or her system level model in C orC++. Another attraction of HLLs is their support for complex mathematical func-tions and similar such utilities. These enable the system analyst to quickly describeand simulate complex features or operations of their system level model withoutbecoming sidetracked or distracted from their main focus by having to write theseutility routines.To assist in the use of C++ for logic design, vendors provide class libraries.3 These extend the capabilities of C++ by including libraries of functions, data types,and other constructs, as well as a simulation kernel. To the user, these additionsmake the C++ model look more like an HDL model while it remains legal C++code. For example, the library will provide a function that implements a wait for anactive clock edge. Other problems solved by the library include interconnectionmethodology, time sequencing, concurrency, data types, performance tracking, anddebugging. Because digital hardware functions operate concurrently, devices suchas the timing wheel (cf. Section 2.9.1) have been invented to solve the concurrencyissue at the gate-level. The C++ library must provide a corresponding capability.Data types that must be addressed in C++ include tri-state logic and odd data buswidths that are not a multiple of 2. After the circuit model has been expressed interms of the library functions and data types, the entire circuit model may then belinked with a simulation kernel.An alternative to C++ for speeding up the simulation process, and reducing theeffort needed to create testbenches, is to extend Verilog and VHDL. The IEEE peri-odically releases new specifications that extend the capabilities of these languages.The release of Verilog-2001, for example, incorporates some of the more attractivefeatures of VHDL, such as the “generate” feature. Vendors are also extending Veri-log and VHDL with proprietary constructs that provide more support for describingoperations at higher levels of abstraction, as well as support for testbench verifica-tion capabilities—for example, constructs that permit complex monitoring actions tobe compressed into just a few lines of code. Oftentimes an activity such as monitor-ing events during simulation—an activity that might take many lines of code in aVerilog testbench, and something that occurs frequently during debug—may beimplemented very efficiently in a language extension. The extensions have theadvantage that they are supersets of Verilog or VHDL; hence the learning curve isquite small for the logic designer already familiar with one of these languages.